SoC Architect

Job Description

We are looking for an experienced SoC Architect to lead the architecture and development of next-generation System-on-Chip (SoC) solutions. This role involves defining system architecture, driving SoC integration, collaborating with cross-functional engineering teams, and ensuring successful silicon delivery from concept through production.

The ideal candidate brings deep expertise in SoC architecture, RTL design, CPU and memory subsystems, low-power design, and technical leadership across large semiconductor programs.

Key Responsibilities

1. Define scalable, high-performance, and power-efficient SoC architectures based on product requirements.
2. Drive system and micro-architecture development for complex SoC platforms.
3. Lead top-level SoC integration including clock/reset architecture, power domains, and subsystem integration.
4. Architect and review CPU, memory, cache hierarchy, and interconnect designs.
5. Collaborate with Design Verification, Physical Design, DFT, Firmware, Software, and Post-Silicon teams throughout the development lifecycle.
6. Guide RTL architecture reviews and ensure reusable, synthesis-friendly design practices.
7. Drive low-power architecture including power gating, clock gating, DVFS, retention, and UPF/CPF implementation.
8. Review verification strategy, functional coverage, assertions, and overall sign-off quality.
9. Support synthesis, timing closure, formal verification, ECO implementation, and silicon bring-up.
10. Mentor engineering teams and provide technical leadership across complex SoC programs.

Required Skills

SoC Architecture

1. System and micro-architecture definition
2. Top-level SoC integration
3. Clock, reset, and power architecture
4. Multi-IP subsystem integration

CPU & Memory

1. ARM / RISC-V / ARC CPU integration
2. Cache hierarchy
3. MMU
4. DDR / LPDDR memory controllers

Interconnect & Interfaces

1. AXI, AHB, APB
2. ACE / CHI (preferred)
3. PCIe
4. USB
5. Ethernet
6. CXL
7. DDR

Low Power Design

1. UPF / CPF
2. Power gating
3. Clock gating
4. DVFS
5. Multi-voltage architecture
6. Retention strategies

RTL & Design

1. SystemVerilog RTL
2. Reusable RTL architecture
3. Synthesis-friendly coding

Sign-off & Verification

1. Synopsys Design Compiler
2. Static Timing Analysis (STA)
3. Timing closure
4. ECO implementation
5. Formal Verification
6. Logical Equivalence Checking (LEC)

DFT & Silicon

1. Scan
2. MBIST
3. JTAG
4. Silicon bring-up
5. Lab debugging
6. Silicon validation

Additional Expertise

1. Chip IO planning
2. Pad ring integration
3. Signal integrity awareness
4. Packaging considerations
5. Hardware/Firmware co-design

Education

1. B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, Computer Science, or equivalent.