Senior Staff Design Verification (DV) Engineer

Job Description

Our client is a global Semiconductor leader and premier R&D GCC, driving cutting-edge innovation in automotive safety, advanced microcontrollers, and edge-AI processing silicon.

Key Professional Responsibilities:

1. Architect, customize, and scale comprehensive constraint-random, coverage-driven verification environments from scratch at block, subsystem, and full-SoC layers.
2. Develop exhaustive test plans, validation strategies, and stimuli frameworks to aggressively verify complex multi-core architectures, interconnected NoC structures, and ultra-high-speed memory nodes.
3. Define, write, and execute functional coverage, structural code coverage, and SystemVerilog Assertions (SVA) to push verification closure metrics to absolute 100%.
4. Collaborate with safety engineering managers to execute automated fault-injection simulations, mathematically validating that hardware safety mechanisms trigger instantly during unexpected failures (ISO 26262 verification).

Core Technical Competencies Required:

1. Verification Frameworks: SystemVerilog, Universal Verification Methodology (UVM), Assertion-Based Verification (SVA).
2. Methodologies: Constrained-random testing, Formal Verification strategies, Gate-Level Simulation (GLS) execution, and Power-Aware Verification (PA-SIM).
3. Simulation Suites: Synopsys VCS, Cadence Xcelium, Questa SIM, and enterprise-grade verification tracking infrastructure.

Confidentiality Assured: At Screen2Hire, we understand the specialized nature of the VLSI ecosystem. If you are a passive candidate exploring the market and want a confidential career mapping discussion before applying formally, please reach out directly to our principal desk at vikas.sharma@screen2hireconsulting.com.