Senior STA Engineer

Job Description

We are hiring a Senior Static Timing Analysis (STA) Engineer for a leading semiconductor engineering services organization. This role offers the opportunity to work on advanced SoC and IP designs, driving timing closure and signoff activities across complex digital designs.

The ideal candidate will have strong expertise in timing analysis, constraint development, MMMC signoff, and close collaboration with RTL, synthesis, DFT, and physical design teams throughout the chip development lifecycle.

Key Responsibilities

1. Develop and maintain timing constraints (SDC) for IP and full-chip SoC designs.
2. Perform comprehensive Static Timing Analysis (STA) using industry-standard timing signoff tools.
3. Drive Multi-Mode Multi-Corner (MMMC) timing closure across functional and test modes.
4. Analyze and resolve setup, hold, recovery, and removal timing violations.
5. Generate and validate SDF files to support gate-level simulations (GLS).
6. Create and maintain timing models including ETM and Liberty-based models.
7. Collaborate with RTL, synthesis, DFT, and physical design teams to achieve timing signoff.
8. Support timing ECO implementation and timing optimization activities.
9. Participate in timing reviews, signoff activities, and SoC integration efforts.
10. Contribute to internal timing methodologies, automation flows, and best practices.

Required Skills & Experience

Static Timing Analysis

1. Strong hands-on experience with:
2. Synopsys PrimeTime
3. Cadence Tempus
4. Expertise in timing signoff methodologies and timing closure.

Timing Constraints & Signoff

1. SDC development and constraint validation.
2. Timing exception handling and constraint optimization.
3. Experience with setup, hold, recovery, removal, and CDC analysis.

MMMC Analysis

1. Strong understanding of Multi-Mode Multi-Corner timing methodologies.
2. Experience driving timing closure across multiple operating conditions and scenarios.

Gate-Level Simulation

1. SDF generation and annotation.
2. GLS setup, execution, and debug support.

DFT & Test Timing

1. Knowledge of scan insertion flows.
2. Experience with test-mode constraints and DFT timing analysis.

Synthesis & Design Flow

1. Exposure to:
2. Synopsys Design Compiler
3. Cadence Genus
4. Understanding of synthesis-to-signoff timing correlation.

Physical Design Collaboration

1. Familiarity with floorplanning, place-and-route flows, and timing ECO implementation.
2. Ability to work closely with physical design teams to resolve timing bottlenecks.

Scripting & Automation

1. Strong scripting skills in:
2. Tcl
3. Perl
4. Shell Scripting

Preferred Qualifications

1. Experience working on advanced-node SoC designs.
2. Exposure to full-chip timing signoff environments.
3. Understanding of low-power design methodologies.
4. Familiarity with version control systems such as Git or Perforce.
5. Experience with tools such as VCS, Verdi, linting, and design management platforms.

What We're Looking For

1. Strong analytical and debugging skills.
2. Ability to independently drive timing closure activities.
3. Excellent collaboration and stakeholder management skills.
4. Experience working in fast-paced semiconductor design environments.
5. Passion for delivering high-quality silicon through robust timing signoff practices.