Semiconductor Opportunity

Senior RTL Design Engineer

Delhi
3 - 5 Years Experience
Full Time
Role Snapshot

Looking for engineers with strong RTL coding experience, microarchitecture understanding, CDC/lint exposure, and synthesis-ready design expertise.

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Job Description

Looking for engineers with strong RTL coding experience, microarchitecture understanding, CDC/lint exposure, and synthesis-ready design expertise.


Responsibilities-

  • Develop microarchitecture and RTL for digital IPs and SoC subsystems.
  • Write clean, synthesizable RTL using Verilog/SystemVerilog.
  • Perform lint, CDC, and synthesis checks to ensure design quality.


Requirements-

  • Strong experience in RTL design and digital logic fundamentals.
  • Hands-on expertise in SystemVerilog / Verilog.
  • Understanding of AMBA protocols such as AXI/AHB/APB.


Job Information
Location Delhi
Experience 3 - 5 Years
Domain RTL Design
Employment Type Full Time
Core Skills
RTL Design Verilog SoC
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