Lead / Senior Engineer – Front-End RTL Synthesis

Job Description

Our client is a global Semiconductor leader and premier R&D GCC, driving cutting-edge innovation in automotive safety, advanced microcontrollers, and edge-AI processing silicon.

Key Professional Responsibilities:

1. Lead logic synthesis, gate-level netlist generation, and structural optimization at the subsystem and chip-top levels to fulfill stringent PPA parameters.
2. Develop, constraint-map, and validate Synopsys Design Constraints (SDC) for high-complexity, multi-clock, and multi-reset domain microcontroller platforms.
3. Execute comprehensive Static Timing Analysis (STA) and timing closure across multiple PVT corners, managing sign-off quality flows (LINT, CDC, RDC).
4. Implement power-aware design architectures using unified UPF/CPF formats, driving formal verification and Logic Equivalency Checking (LEC) to ensure zero architectural drift from RTL to netlist.

Core Technical Competencies Required:

1. EDA Tools: Synopsys Design Compiler (DC/FC), Cadence Genus, PrimeTime (STA), Formality/Conformal (LEC).
2. Methodologies: Power-aware structural logic synthesis, Low-power architectures (UPF/CPF), Hierarchical timing budgeting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) sign-offs.
3. Automation Architecture: Advanced Tcl, Perl, and Python scripting for complex EDA tool customization.

Confidentiality Assured: At Screen2Hire, we understand the specialized nature of the VLSI ecosystem. If you are a passive candidate exploring the NCR market and want a confidential career mapping discussion before applying formally, please reach out directly to our principal desk at vikas.sharma@screen2hireconsulting.com.