Semiconductor Opportunity

DFT Lead / Manager

Bangalore, Hyderabad, Chennai
7 - 12 Years Experience
Full Time
Role Snapshot

Looking for professionals with strong hands-on exposure in ATPG, MBIST, SAF/TDF, Tessent/TestKompress and silicon debug environments. Opportunity to work on advanced semiconductor programs involving block-level or full-chip DFT flows.

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Job Description

This role focuses on DFT architecture, ATPG, MBIST verification, and production test readiness for complex ASIC programs. The ideal candidate brings strong silicon validation experience, hands-on tool expertise, and the ability to collaborate across design, product, and test engineering teams.

Role Responsibilities

  • Work closely with ASIC design teams to ensure DFT architecture, design rule compliance, and coverage targets are achieved.
  • Develop manufacturing-ready ATPG patterns for stuck-at fault (SAF) and transition delay fault (TDF) models using on-chip compression techniques.
  • Execute MBIST verification, including memory repair validation, and generate associated test patterns using Mentor test tools.
  • Run ATPG (SAF/TDF) and MBIST verification across unit-delay and min/max timing-corner simulations.
  • Partner with Product and Test Engineering teams to deliver production test patterns for ATE.
  • Support post-silicon debug, failure analysis, and timely resolution of DFT-related issues.
  • Prepare diagnostic collateral for ATPG and MBIST and support ATE bring-up activities.
  • Build and maintain automation scripts to improve efficiency and execution quality.

Candidate Profile

  • Bachelor's or Master's degree in Computer Science, Electrical Engineering, or Electronics Engineering.
  • 7 to 12 years of experience in ASIC/DFT simulation and silicon validation.
  • Hands-on experience with at least one full-chip DFT implementation or strong expertise in block-level ATPG and MBIST.
  • Strong understanding of DFT concepts, pattern simulation, silicon debug, and yield improvement.
  • Hands-on expertise in ATPG execution, fault coverage analysis, and pattern validation.
  • Strong knowledge of memory verification, repair analysis, and memory failure root-cause analysis.
  • Experience with one or more of the following tools: TestKompress for ATPG, Mentor ETVerify for MBIST, and VCS preferred or ModelSim for simulation.
  • Scripting capability in Perl, shell, or similar languages is an advantage.
  • Strong communication skills and the ability to work effectively in a dynamic, global team environment.
  • Quick learner with the ability to adapt to new tools and methodologies.
  • Proven ability to manage multiple high-priority designs in parallel.

Key Skills

  • ATPG (SAF / TDF)
  • MBIST Verification & Repair Analysis
  • Tessent / TestKompress / ETVerify
  • Silicon Debug & ATE Support
  • VCS / ModelSim
  • Perl / Shell Scripting




Job Information
Location Bangalore, Hyderabad, Chennai
Experience 7 - 12 Years
Domain DFT
Employment Type Full Time
Core Skills
ATPG (SAF / TDF) MBIST VCS
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