DFT Engineers / DFT Leads

Job Description

We are looking for experienced DFT Engineers and DFT Leads for opportunities with leading semiconductor design and engineering organizations in Bangalore. The roles involve end-to-end Design for Test (DFT) implementation for complex ASICs, SoCs and MCUs, covering DFT architecture, scan, ATPG, MBIST, verification, sign-off and silicon bring-up.

Depending on experience, candidates may contribute as hands-on DFT engineers or take ownership of DFT architecture, methodology and technical execution.

Key Responsibilities

1. Define and implement DFT architecture and strategies for complex ASIC, SoC and MCU designs.
2. Drive Scan Insertion, Scan Compression, Scan Stitching, ATPG, MBIST and JTAG implementation.
3. Perform fault simulation, DFT verification, gate-level validation and scan debug to achieve coverage and sign-off targets.
4. Debug and resolve ATPG, scan chain and GLS issues while improving overall testability and test efficiency.
5. Work closely with RTL, Physical Design, STA, Verification and Test Engineering teams for successful DFT closure.
6. Support silicon bring-up, ATE correlation and post-silicon debug where required.
7. Develop and improve DFT automation flows using Tcl, Python and/or Perl.
8. For senior/lead positions, drive DFT architecture, hierarchical test strategy, technical reviews and methodology improvements.

Required Skills

1. 7–15+ years of hands-on Design for Test (DFT) experience in ASIC/SoC development.
2. Strong experience in Scan Insertion, Scan Compression, ATPG, MBIST and Fault Simulation.
3. Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFTMAX, DFT Compiler, Cadence Modus, or equivalent.
4. Experience with JTAG / Boundary Scan and DFT verification/debug methodologies.
5. Good understanding of gate-level simulation, scan validation and DFT sign-off.
6. Working knowledge of Verilog and/or VHDL.
7. Scripting experience using Tcl, Python and/or Perl.
8. Strong debugging, analytical and cross-functional collaboration skills.

Additional Experience Preferred

Experience in one or more of the following would be advantageous: hierarchical DFT flows, IEEE 1149.1 / IEEE 1500, low-power DFT for multi-voltage or clock-gated designs, silicon bring-up, ATE correlation, production test and advanced-node SoC development.

Qualification

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Science or a related discipline.