Semiconductor Opportunity

Design Verification Engineer

Hyderabad
5 - 10 Years Experience
Full Time
Role Snapshot

Hiring DV engineers with hands-on UVM environment development, protocol verification, debugging, and functional coverage experience.

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Job Description

Hiring DV engineers with hands-on UVM environment development, protocol verification, debugging, and functional coverage experience.

Key Responsibilities

Collaborate with verification teams for debug and coverage closure. Support integration, timing closure, and low-power implementation activities. Participate in design reviews and contribute to methodology improvements.

Required Skills & Experience

Understanding of AMBA protocols such as AXI/AHB/APB. Exposure to CDC, lint, STA, and synthesis flows. Experience with low-power design methodologies is an advantage.
Job Information
Location Hyderabad
Experience 5 - 10 Years
Domain Design Verification
Employment Type Full Time
Core Skills
Microarchitecture CDC
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